Glossary:PLL: Difference between revisions

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A phase locked loop or PLL is a circuit containing a variable [[Glossary:Frequency|frequency]] [[Glossary:Oscillator|oscillator]] which, by means of a feedback loop, is kept locked in phase with an input signal. The oscillator output may be fed into a frequency divider before being compared with the input signal, so locking the oscillator to a numerical multiple of the input frequency.
A phase locked loop or PLL is a circuit in which the [[Glossary:Frequency|frequency]] of a variable frequency [[Glossary:Oscillator|oscillator]] is locked to a reference frequency or to a frequency with a simple numerical relationship to it. The many applications include digital tuning in a radio.

Revision as of 16:49, 31 March 2019

A phase locked loop or PLL is a circuit in which the frequency of a variable frequency oscillator is locked to a reference frequency or to a frequency with a simple numerical relationship to it. The many applications include digital tuning in a radio.